1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and, more particularly, to a method of manufacturing a semiconductor device in which a plurality of contact holes having largely different depths can be formed simultaneously to provide good electrical characteristics.
2. Description of the Prior Art
The first prior art concerning a contact formation process known as one of semiconductor device manufacturing methods will be described with reference to the sectional view shown in FIG. 1.
The semiconductor device having a section shown in FIG. 1 shows a state after it is manufactured in accordance with the following manufacturing method.
A field oxide film 301 serving as an isolation region, and a gate electrode 302 are sequentially formed on a silicon substrate by patterning with a known scheme. An oxide film is formed on the entire surface of the resultant structure, and is etched back by dry etching back to form a side wall 303 on the side wall of the gate electrode 302.
Subsequently, a diffusion layer 304 is formed by known ion implantation and annealing. A first interlevel insulating film 305 is formed on the entire surface, and its upper surface is planarized by CMP as a known planarization scheme. After the planarization, a prospective upper interconnection film is deposited with a known scheme and patterned to form an upper interconnection 306. A second interlevel insulating film 307 is deposited on the entire surface, and its upper surface is planarized by CMP again. A resist (not shown) for forming contact holes is formed on the planarized second interlevel insulating film 307 and is patterned by known photolithography. After contact holes 308a and 308b are formed by dry etching, the resist is removed. A contact 308 is formed in each of the contact holes 308a and 308b.
The second prior art concerning the contact formation process will be described with reference to the sectional views shown in FIGS. 2A and 2B.
In the semiconductor device having sections shown in FIGS. 2A and 2B, the same process as that described concerning FIG. 1 described above is performed until formation of a diffusion layer 404 (corresponding to the diffusion layer 304 of FIG. 1). The process of FIGS. 2A and 2B is different from that described with reference to FIG. 1 in that after the diffusion layer 404 is formed, a nitride film 409 is formed on the entire surface of the structure. After that, the same process as that described in FIG. 1 is performed. The nitride film 409 is formed on the entire surface in this manner after the diffusion layer 404 is formed. If the diffusion layer 404 and a gate electrode 402 form a step that allows formation of contact holes 408a and 408b on them, as shown in FIGS. 2A and 2B, then contact holes 408a and 408b can be respectively formed on the diffusion layer 404 and gate electrode 402 simultaneously with a sufficiently large process margin. In this case, when the selectivity of dry etching of the nitride film 409 with respect to the oxide film (interlevel insulating film) is increased, contact holes can be formed once to reach the nitride film 409, as shown in FIG. 2A. After that, the nitride film 409 is etched, so that the two contact holes 408a and 408b having different depths can be completed, as shown in FIG. 2B. A contact 408 is formed in each of the contact holes 408a and 408b.
As semiconductor devices shrink in feature size and increase in integration degree, a plurality of contact holes having largely different depths must be formed, leading to a problem.
In the prior art described with reference to FIG. 1, etching for the contact hole 308b that reaches the upper interconnection 306 ends sooner than for the contact hole 308a that reaches the diffusion layer 304. Therefore, while etching in the process of forming the contact hole 308a, the upper interconnection 306 may be etched either partially or entirely so the contact hole 308b may extend through the upper interconnection 306. This leads to disconnection of the contact portion and an increase in contact resistance, so good electrical characteristics cannot be obtained.
The third prior art concerning the contact formation process will be described with reference to the sectional view shown in FIG. 3. A contact hole 508c as shown in FIG. 3 that reaches an upper interconnection 506 must be formed to have a depth largely different from those of other contact holes 508a and 508b. It is accordingly difficult to form contact holes for a diffusion layer 504, a gate electrode 502, and the upper interconnection 506 simultaneously. A contact 508 is formed in each of the contact holes 508a, 508b, and 508c.
Under these circumstances, a method that can form a plurality of contacts having largely different depths is sought for. As a countermeasure against the above problem, it is conventionally known to form a nitride film or the like on the upper surface of an interconnection.
In a hybrid DRAM/Logic semiconductor product in which a self-align-silicide or salicide process is performed, if a nitride film is formed on an interconnection, the salicide process cannot be done on the interconnection.